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Upcoming Conferences

Books

B9 Zhixin Pan and Prabhat Mishra, Explainable AI for Cybersecurity, ISBN: 978-3-031-46478-2, Springer Nature, 2023.
B8 Prabhat Mishra and Subodha Charles (Editors), Network-on-Chip Security and Privacy, ISBN: 978-3-030-69130-1, Springer, 2021.
B7 Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, System-on-Chip Security Validation and Verification, ISBN: 978-3-030-30596-3, Springer, 2019.
B6 Prabhat Mishra and Farimah Farahmandi (Editors), Post-Silicon Validation and Debug, ISBN: 978-3-319-98115-4, Springer, 2018.
B5 Prabhat Mishra, Swarup Bhunia and Mark Tehranipoor (Editors), Hardware IP Security and Trust, ISBN: 978-3-319-49024-3, Springer, 2017.
B4 Mingsong Chen, Xiaoke Qin, Heon-Mo Koo and Prabhat Mishra, System-Level Validation: High-Level Modeling and Directed Test Generation Techniques, ISBN: 978-1-4614-1358-5, Springer, August 2012.
B3 Weixun Wang, Prabhat Mishra and Sanjay Ranka, Dynamic Reconfiguration in Real-Time Systems - Energy, Performance, Reliability and Thermal Perspectives, ISBN: 978-1-4614-0277-0, Springer, July 2012.
B2 Prabhat Mishra and Nikil Dutt (Editors), Processor Description Languages - Applications and Methodologies, Morgan Kaufmann, ISBN: 978-0-12-374287-2, June 2008.
B1 Prabhat Mishra and Nikil Dutt, Functional Verification of Programmable Embedded Architectures - A Top-Down Approach, Springer, ISBN: 0-387-26143-5, July 2005.

Journal Articles

J78 Sahan Sanjaya, Hasini Witharana, and Prabhat Mishra, Assertion-Based Validation using Clustering and Dynamic Refinement of Hardware Checkers, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2024.
J77 Hansika Weerasena and Prabhat Mishra, Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators, ACM Transactions on Embedded Computing Systems (TECS), 2024.
J76 Hasini Witharana, Hansika Weerasena and Prabhat Mishra, Formal Verification of Virtualization-based Trusted Execution Environments, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
J75 Hansika Weerasena and Prabhat Mishra, Breaking On-Chip Communication Anonymity using Flow Correlation Attacks, ACM Journal on Emerging Technologies in Computing Systems (JETC), 2024.
J74 Aruna Jayasena and Prabhat Mishra, HIVE: Scalable Hardware-Firmware Co-Verification using Scenario-based Decomposition and Automated Hint Extraction, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
J73 Hasini Witharana, Aruna Jayasena and Prabhat Mishra, Incremental Concolic Testing of Register-Transfer Level Designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2024.
J72 Zachery Utt, Daniel Volya and Prabhat Mishra, Quantum Measurement Classification using Statistical Learning, ACM Transactions on Quantum Computing (TQC), 2024.
J71 Zhixin Pan and Prabhat Mishra, TD-Zero: Automatic Golden-Free Hardware Trojan Detection using Zero-Shot Learning, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
J70 Daniel Volya and Prabhat Mishra, State Preparation on Quantum Computers via Quantum Steering, IEEE Transactions on Quantum Engineering (TQE), 2024.
J69 Aruna Jayasena and Prabhat Mishra, Directed Test Generation for Hardware Validation: A Survey, ACM Computing Surveys (CSUR), 2023.
J68 Hansika Weerasena and Prabhat Mishra, Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2023.
J67 Aruna Jayasena, Emma Andrews and Prabhat Mishra, TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2023.
J66 Aruna Jayasena and Prabhat Mishra, Scalable Detection of Hardware Trojans using ATPG-based Activation of Rare Events, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.
J65 Zhixin Pan and Prabhat Mishra, AI Trojan Attack for Evading Machine Learning-based Detection of Hardware Trojans, IEEE Transactions on Computers (TC), 2023.
J64 Meenu Dey, Moumita Patra and Prabhat Mishra, Efficient Detection and Localization of DoS Attacks in Heterogeneous Vehicular Networks, IEEE Transactions on Vehicular Technology (TVT), 2022.
J63 Aruna Jayasena, Binod Kumar, Subodha Charles, Hasini Witharana and Prabhat Mishra, Network-on-Chip Trust Validation using Security Assertions, Springer Journal of Hardware and Systems Security (HASS), 2022.
J62 Hasini Witharana, Aruna Jayasena, Andrew Whigham and Prabhat Mishra, Automated Generation of Security Assertions for RTL Models, ACM Journal on Emerging Technologies in Computing Systems (JETC), 2022.
J61 Chamika Sudusinghe, Subodha Charles, Sapumal Ahangama and Prabhat Mishra, Eavesdropping Attack Detection using Machine Learning in Network-on-Chip Architectures, IEEE Design & Test (D&T), 2022.
J60 Zhixin Pan and Prabhat Mishra, A Survey on Hardware Vulnerability Analysis using Machine Learning, IEEE Access (Access), 2022.
J59 Subodha Charles, Vincent Bindschaedler and Prabhat Mishra, Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2022.
J58 Zhixin Pan, Jennifer Sheldon and Prabhat Mishra, Hardware-Assisted Malware Detection and Localization using Explainable Machine Learning, IEEE Transactions on Computers (TC), 2022.
J57 Priyanka Panigrahi, Vemuri Sahithya, Chandan Karfa, and Prabhat Mishra, Secure Register Allocation for Trusted Code Generation, IEEE Embedded Systems Letters (ESL), 2022.
J56 Hasini Witharana, Yangdi Lyu, Subodha Charles and Prabhat Mishra, A Survey on Assertion-based Hardware Verification, ACM Computing Surveys (CSUR), 2022.
J55 Abhijit Das, John Jose and Prabhat Mishra, Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 29(9), pages 1675-1679, 2021.
J54 Subodha Charles and Prabhat Mishra, A Survey of Network-on-Chip Security Attacks and Countermeasures, ACM Computing Surveys (CSUR), 54(5), article 101, pages 1-36, 2021.
J53 Hasini Witharana, Yangdi Lyu and Prabhat Mishra, Directed Test Generation for Activation of Security Assertions in RTL Models, ACM Transactions on Design Automation of Electronic Systems (TODAES), 26(4), article 26, pages 1-28, 2021.
J52 Yangdi Lyu and Prabhat Mishra, MaxSense: Side-Channel Sensitivity Maximization for Trojan Detection using Statistical Test Patterns, ACM Transactions on Design Automation of Electronic Systems (TODAES), 26(3), article 22, pages 1-21, 2021.
J51 Yangdi Lyu and Prabhat Mishra, Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 40(7), pages 1287-1300, 2021.
J50 Subodha Charles and Prabhat Mishra, Reconfigurable Network-on-Chip Security Architecture, ACM Transactions on Design Automation of Electronic Systems (TODAES), 25(6), article 53, pages 1-25, 2020.
J49 Yangdi Lyu and Prabhat Mishra, Scalable Concolic Testing of RTL Models, IEEE Transactions on Computers (TC), 70(7), pages 979-991, 2021.
J48 Aisharjya Sarkar, Prabhat Mishra and Tamer Kahveci, Data Perturbation and Recovery of Time Series Gene Expression Data, IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB), 19(2), pages 830-842, 2022.
J47 Subodha Charles, Yangdi Lyu and Prabhat Mishra, Real-time Detection and Localization of Distributed DoS Attacks in NoC based SoCs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 39(12), pages 4510-4523, 2020.
J46 Subodha Charles, Alif Ahmed, Umit Ogras and Prabhat Mishra, Efficient Cache Reconfiguration using Machine Learning in NoC-based Many-Core CMPs, ACM Transactions on Design Automation of Electronic Systems (TODAES), 24(6), Article 60, September 2019.
J45 Alif Ahmed, Yuanwen Huang and Prabhat Mishra, Cache Reconfiguration using Machine Learning for Vulnerability-aware Energy Optimization, ACM Transactions on Embedded Computing Systems (TECS), 8(2), Article 15, March 2019.
J44 Farimah Farahmandi and Prabhat Mishra, Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits, IEEE Transactions on Computers (TC), 68(2), pages 182-197, February 2019.
J43 Yuanwen Huang, Swarup Bhunia and Prabhat Mishra, Scalable Test Generation for Trojan Detection using Side Channel Analysis, IEEE Transactions on Information Forensics & Security (TIFS), 13(11), pages 2746-2760, May 2018.
J42 Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte and Mark Tehranipoor, Security-aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), May 2018.
J41 Yuanwen Huang and Prabhat Mishra, Vulnerability-aware Energy Optimization for Reconfigurable Caches in Multitasking Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(5), pages 809-821, May 2019.
J40 Yangdi Lyu, Xiaoke Qin, Mingsong Chen and Prabhat Mishra, Directed Test Generation for Validation of Cache Coherence Protocols, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), February 2018.
J39 Kamran Rahmani and Prabhat Mishra, Feature-based Signal Selection for Post-silicon Debug using Machine Learning, IEEE Transactions on Emerging Topics in Computing (TETC), December 2017.
J38 Yangdi Lyu and Prabhat Mishra, A Survey of Side Channel Attacks on Caches and Countermeasures, Springer Journal of Hardware and Systems Security (HASS), issue 2, pages 33-50, 2018.
J37 Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra and Yier Jin, Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 25(12), pages 3390-3400, December 2017.
J36 Ujjwal Gupta, Chetan Patil, Ganapati Bhat, Prabhat Mishra and Umit Ogras, DyPO: Dynamic Pareto Optimal Configuration Selection for Heterogeneous MpSoCs, ACM Transactions on Embedded Computing Systems (TECS), 16(5), pages 123:1-123:20, October 2017.
J35 Kamran Rahmani, Sandip Ray and Prabhat Mishra, Post-silicon Trace Signal Selection Using Machine Learning Techniques, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 25(2), pages 570-580, February 2017.
J34 Prabhat Mishra, Ronny Morad, Avi Ziv and Sandip Ray, Post-silicon Validation in the SoC Era: A Tutorial Introduction, IEEE Design & Test (D&T), 34(3), pages 68-92, June 2017.
J33 Yuanwen Huang and Prabhat Mishra, Trace Buffer Attack on the AES Cipher, Springer Journal of Hardware and Systems Security (HASS), 1(1), pages 68-84, 2017.
J32 Mingsong Chen, Xinqian Zhang, Geguang Pu, Xin Fu and Prabhat Mishra, Efficient Resource Constrained Scheduling using Parallel Structure-Aware Pruning Techniques, IEEE Transactions on Computers (TC), 65(7), pages 2059-2073, July 2016.
J31 Kamran Rahmani, Sudhi Proch and Prabhat Mishra, Efficient Selection of Trace and Scan Signals for Post-Silicon Debug, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 24(1), 313-323, 2016.
J30 Mingsong Chen, Xiaoke Qin and Prabhat Mishra, Learning-Oriented Property Decomposition for Automated Generation of Directed Tests, Springer Journal of Electronic Testing (JETTA), 30(3), pages 287-306, 2014.
J29 Kanad Basu and Prabhat Mishra, Restoration-Aware Trace Signal Selection for Post Silicon Validation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 21(4), pages 605-613, April 2013.
J28 Xiaoke Qin, Weixun Wang and Prabhat Mishra, TCEC: Temperature- and Energy-Constrained Scheduling in Real-Time Multitasking Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 31(8), pages 1159-1168, August 2012.
J27 Weixun Wang, Sanjay Ranka and Prabhat Mishra, Energy-Aware Dynamic Slack Allocation for Real-Time Multitasking Systems, Elsevier Sustainable Computing: Informatics and Systems (SUSCOM), 2(3), pages 128-137, September 2012.
J26 Kanad Basu, Chetan Murthy and Prabhat Mishra, Bitmask aware Compression of NISC Control Words, Elsevier Integration, the VLSI Journal (INTEGRATION), 46(2), pages 131-41, March 2012.
J25 Xiaoke Qin and Prabhat Mishra, Directed Test Generation for Validation of Multicore Architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 17, no 3, article 24, 21 pages, June 2012.
J24 Hadi Hajimiri, Kamran Rahmani and Prabhat Mishra, Compression-Aware Dynamic Cache Reconfiguration for Embedded Systems, Elsevier Sustainable Computing: Informatics and Systems (SUSCOM), volume 2, issue 2, pages 71-80, June 2012.
J23 Weixun Wang, Prabhat Mishra and Ann-Gordon Ross, Dynamic Cache Reconfiguration for Soft Real-Time Systems, ACM Transactions on Embedded Computing Systems (TECS), volume 11, issue 2, article 28, 31 pages, July 2012.
J22 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Automatic RTL Test Generation from SystemC TLM Specifications, ACM Transactions on Embedded Computing Systems (TECS), 11(2), article 38, July 2012.
J21 Mingsong Chen and Prabhat Mishra, Property Learning Techniques for Efficient Generation of Directed Tests, IEEE Transactions on Computers (TC), 60(6), pages 852-864, June 2011.
J20 Weixun Wang and Prabhat Mishra, System-Wide Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), volume 20, issue 5, pages 902 - 910, May 2012.
J19 Weixun Wang and Prabhat Mishra, Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems, Journal of Low Power Electronics (JOLPE), 7(1), pages 17-28, February 2011.
J18 Weixun Wang, Sanjay Ranka and Prabhat Mishra, Energy-Aware Dynamic Reconfiguration Algorithms for Real-Time Multitasking Systems, Elsevier Sustainable Computing: Informatics and Systems (SUSCOM), 1(1), pages 35-45, March 2011.
J17 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Efficient Test Case Generation for Validation of UML Activity Diagrams, Springer Design Automation for Embedded Systems (DAES), 14(2), pages 105-130, 2010.
J16 Xiaoke Qin, Chetan Murthy and Prabhat Mishra, Decoding-aware Compression of FPGA Bitstreams, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 19(3), pages 411-419, March 2011.
J15 Mingsong Chen and Prabhat Mishra, Functional Test Generation using Efficient Property Clustering and Learning Techniques, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(3), 396-404, 2010.
J14 Kanad Basu and Prabhat Mishra, Test Data Compression using Efficient Bitmask and Dictionary Selection Methods, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), volume 18, issue 9, pages 1277-1286, 2010.
J13 Xiaoke Qin and Prabhat Mishra, A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 28, no 8, pages 1224-1236, August 2009.
J12 Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Design and Property Decomposition Techniques, ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 4, article 32, July 2009.
J11 Seok-Won Seong and Prabhat Mishra, Bitmask-Based Code Compression for Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 27, no 4, pages 673-685, April 2008.
J10 Mehrdad Reshadi, Prabhat Mishra, and Nikil Dutt, Hybrid Compiled Simulation: An Efficient Technique for Instruction-Set Architecture Simulation, ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 3, 27 pages, Article 20, April 2009.
J9 Prabhat Mishra and Nikil Dutt, Specification-driven Directed Test Generation for Validation of Pipelined Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 13, no 2, 36 pages, article 42, July 2008.
J8 Prabhat Mishra, Aviral Shrivastava, and Nikil Dutt, Architecture Description Language (ADL)-driven Software Toolkit generation for Architectural Exploration of Programmable SOCs, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 11, no 3, pages 626-658, July 2006.
J7 Mehrdad Reshadi, Prabhat Mishra and Nikil Dutt, A Retargetable Framework for Instruction-Set Architecture Simulation, ACM Transactions on Embedded Computing Systems (TECS), volume 5, no 2, pages 431-452, May 2006.
J6 Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, and Magdy Abadir, A Methodology for Validation of Microprocessors using Symbolic Simulation, Inderscience International Journal of Embedded Systems (IJES), volume 1, no 1/2, pages 14-22, 2005.
J5 Prabhat Mishra and Nikil Dutt, Architecture Description Languages for Programmable Embedded Systems, IEE Proceedings on Computers and Digital Techniques (CDT), Special issue on Embedded Microelectronic Systems: Status and Trends, volume 152, no 3, pages 285--297, May 2005.
J4 Prabhat Mishra, Mahesh Mamidipaka and Nikil Dutt, Processor-Memory Co-Exploration using an Architecture Description Language, ACM Transactions on Embedded Computing Systems (TECS), volume 3, number 1, pages 140-162, February 2004.
J3 Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, and Magdy Abadir, A Top-Down Methodology for Validation of Microprocessors, IEEE Design and Test of Computers (Design&Test), Special Issue on Functional Verification and Testbench Generation, volume 21, number 2, pages 122-131, 2004.
J2 Prabhat Mishra and Nikil Dutt, Modeling and Validation of Pipeline Specifications, ACM Transactions on Embedded Computing Systems (TECS), volume 3, number 1, pages 114-139, February 2004.
J1 Prabhat Mishra, Nikil Dutt, and Hiroyuki Tomiyama, Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications, Kluwer Design Automation for Embedded Systems (DAES), volume 8, number 2, pages 249-265, 2003.

Referred Conference Papers with Archival Proceedings

C145 Daniel Volya and Prabhat Mishra, Quantum Benchmarking via Random Dynamical Quantum Maps, IEEE International Conference on Quantum Computing and Engineering (QCE), Montreal, Canada, September 15-20, 2024.
C144 Sahan Sanjaya, Daniel Volya and Prabhat Mishra, Variational Quantum Algorithms via Measurement-Induced Passive Steering, IEEE International Conference on Quantum Computing and Engineering (QCE), Montreal, Canada, September 15-20, 2024.
C143 Daniel Volya, Andrey Nikitin and Prabhat Mishra, Fast Quantum Process Tomography via Riemannian Gradient Descent, IEEE International Conference on Quantum Computing and Engineering (QCE), Montreal, Canada, September 15-20, 2024.
C142 Hasini Witharana, Hansika Weerasena and Prabhat Mishra, Formal Verification of Virtualization-based Trusted Execution Environments, ACM/IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Raleigh, North Carolina, September 29 - October 4, 2024.
C141 Hasini Witharana, Debapriya Chatterjee and Prabhat Mishra, Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, May 6-9, 2024.
C140 Hansika Weerasena and Prabhat Mishra, Lightweight Multicast Authentication in NoC-based SoCs, IEEE International Symposium on Quality Electronic Design (ISQED), San Francisco, California, April 3-5, 2024.
C139 Aruna Jayasena, Richard Bachmann and Prabhat Mishra, EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves, Design Automation and Test in Europe (DATE), Valencia, Spain, March 25-27, 2024.
C138 Aruna Jayasena and Prabhat Mishra, Design for Trust utilizing Rareness Reduction, International Conference on VLSI Design (VLSID), Kolkata, India, January 6-10, 2024.
C137 Hasini Witharana, Daniel Volya and Prabhat Mishra, QcAssert: Quantum Device Testing with Concurrent Assertions, Asia and South Pacific Design Automation Conference (ASPDAC), South Korea, January 22 - 25, 2024.
C136 Daniel Volya and Prabhat Mishra, Quantum Steering of Surface Error Correcting Codes, IEEE International Conference on Quantum Computing and Engineering (QCE), Bellevue, Washington, September 17-22, 2023.
C135 Daniel Volya, Zhixin Pan and Prabhat Mishra, Feedback-based Steering for Quantum State Preparation, IEEE International Conference on Quantum Computing and Engineering (QCE), Bellevue, Washington, September 17-22, 2023.
C134 Daniel Volya, Tao Zhang, Nashmin Alam, Mark Tehranipoor and Prabhat Mishra, Towards Secure Classical-Quantum Systems, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, May 1-4, 2023.
C133 Hasini Witharana, Sahan Sanjaya and Prabhat Mishra, Dynamic Refinement of Hardware Assertion Checkers, Design Automation and Test in Europe (DATE), Antwerp, Belgium, April 17-19, 2023.
C132 Zachery Utt, Daniel Volya and Prabhat Mishra, Quantum Measurement Discrimination using Cumulative Distribution Functions, Design Automation and Test in Europe (DATE), Antwerp, Belgium, April 17-19, 2023.
C131 Zhixin Pan and Prabhat Mishra, Hardware Trojan Detection using Shapley Ensemble Boosting, Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 16 - 19, 2023. Nominated for Best Paper Award
C130 Daniel Volya and Prabhat Mishra, Quantum Data Compression for Efficient Generation of Control Pulses, Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 16 - 19, 2023.
C129 Hasini Witharana and Prabhat Mishra, Speculative Load Forwarding Attack on Modern Processors, International Conference on Computer-Aided Design (ICCAD), October 30 - November 3, 2022.
C128 Aruna Jayasena, Khushboo Rani and Prabhat Mishra, Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks, IEEE International Conference on Computer Design (ICCD), Lake Tahoe, October 23-26, 2022.
C127 Daniel Volya and Prabhat Mishra, Modeling of Noisy Quantum Circuits using Random Matrix Theory, Special Session on Noise-aware Quantum Synthesis and Compilation in IEEE International Conference on Computer Design (ICCD), Lake Tahoe, October 23-26, 2022.
C126 Chamika Sudusinghe, Subodha Charles, Sapumal Ahangama and Prabhat Mishra, Eavesdropping Attack Detection using Machine Learning in Network-on-Chip Architectures, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), October 7-14, 2022.
C125 Zhixin Pan and Prabhat Mishra, Design of AI Trojans for Evading Machine Learning-based Detection of Hardware Trojans, Design Automation and Test in Europe (DATE), Antwerp, Belgium, March 14-15, 2022.
C124 Zhixin Pan and Prabhat Mishra, Hardware Acceleration of Explainable Machine Learning, Design Automation and Test in Europe (DATE), Antwerp, Belgium, March 14-15, 2022.
C123 Hansika Weerasena, Subodha Charles and Prabhat Mishra, Lightweight Encryption using Chaffing and Winnowing with All-or-Nothing Transform for Network-on-Chip Architectures, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, December 12-15, 2021.
C122 Zhixin Pan and Prabhat Mishra, Automated Detection of Spectre and Meltdown Attacks using Explainable Machine Learning, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, December 12-15, 2021.
C121 Chamika Sudusinghe, Subodha Charles and Prabhat Mishra, Denial-of-Service Attack Detection using Machine Learning in Network-on-Chip Architectures, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), October 8-15, 2021.
C120 Zhixin Pan and Prabhat Mishra, Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural Networks, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021.
C119 Daniel Volya and Prabhat Mishra, Quantum Spectral Clustering of Mixed Graphs, ACM/IEEE Design Automation Conference (DAC), 2021.
C118 Meenu Dey, Moumita Patra and Prabhat Mishra, Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular Networks, Design Automation and Test in Europe (DATE), Grenoble, France, February 1-5, 2021.
C117 Zhixin Pan, Jennifer Sheldon, Chamika Sudusinghe, Subodha Charles and Prabhat Mishra, Hardware-Assisted Malware Detection using Machine Learning, Special Session on Hardware-based Malware Detectors in Design Automation and Test in Europe (DATE), Grenoble, France, February 1-5, 2021.
C116 Zhixin Pan and Prabhat Mishra, Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning, Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 18 - 21, 2021.
C115 Daniel Volya and Prabhat Mishra, Impact of Noise on Quantum Algorithms in NISQ Systems, Special Session on Reliable Quantum Computing using Noise Intermediate-Scale Quantum Systems in IEEE International Conference on Computer Design (ICCD), October 18-21, 2020.
C114 Zhixin Pan, Jennifer Sheldon and Prabhat Mishra, Hardware-Assisted Malware Detection using Explainable Machine Learning, IEEE International Conference on Computer Design (ICCD), October 18-21, 2020.
C113 Zhixin Pan, Jennifer Sheldon and Prabhat Mishra, Test Generation using Reinforcement Learning for Delay-based Side Channel Analysis, IEEE/ACM International Conference on Computer Aided Design (ICCAD), November 2-5, 2020.
C112 Manju R, Abhijit Das, John Jose and Prabhat Mishra, SECTAR: Secure NoC using Trojan Aware Routing, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), September 24-25, 2020.
C111 Subodha Charles and Prabhat Mishra, Lightweight and Trust-aware Routing in NoC Based SoCs, IEEE Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, July 6-8, 2020.
C110 Subodha Charles and Prabhat Mishra, Securing Network-on-Chip Using Incremental Cryptography, IEEE Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, July 6-8, 2020.
C109 Yuanwen Huang and Prabhat Mishra, Vulnerability-aware Dynamic Reconfiguration of Partially Protected Caches, IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, March 25-26, 2020.
C108 Subodha Charles, Megan Logan and Prabhat Mishra, Lightweight Anonymous Routing in NoC based SoCs, Design Automation and Test in Europe (DATE), Grenoble, France, March 9 - 13, 2020.
C107 Yangdi Lyu and Prabhat Mishra, Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis, Design Automation and Test in Europe (DATE), Grenoble, France, March 9 - 13, 2020.
C106 Yangdi Lyu and Prabhat Mishra, Automated Trigger Activation by Repeated Maximal Clique Sampling, Asia and South Pacific Design Automation Conference (ASPDAC), Beijing, China, January 13 - 16, 2020.
C105 Yangdi Lyu and Prabhat Mishra, Automated Test Generation for Activation of Assertions in RTL Models, Asia and South Pacific Design Automation Conference (ASPDAC), Beijing, China, January 13 - 16, 2020.
C104 Jonathan Cruz, Prabhat Mishra and Swarup Bhunia, The Metric Matters: How to Measure Trust, Design Automation Conference (DAC), Las Vegas, June 2 - 6, 2019.
C103 Yangdi Lyu and Prabhat Mishra, Efficient Test Generation for Trojan Detection using Side Channel Analysis, Design Automation and Test in Europe (DATE), Florence, Italy, March 25 - 29, 2019.
C102 Subodha Charles, Yangdi Lyu, Prabhat Mishra, Real-time Detection and Localization of DoS Attacks in NoC based SoCs, Design Automation and Test in Europe (DATE), Florence, Italy, March 25 - 29, 2019.
C101 Yangdi Lyu, Alif Ahmed and Prabhat Mishra, Automated Activation of Multiple Targets in RTL Models using Concolic Testing, Design Automation and Test in Europe (DATE), Florence, Italy, March 25 - 29, 2019. Nominated for Best Paper Award
C100 Subodha Charles, Hadi Hajimiri and Prabhat Mishra, Proactive Thermal Management using Memory-based Computing in Multicore Architectures, International Green and Sustainable Computing Conference (IGSC), Pittsburgh, October 22-24, 2018.
C99 Subodha Charles, Chetal Patil, Umit Ogras and Prabhat Mishra, Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, October 4-5, 2018.
C98 Alif Ahmed, Farimah Farahmandi, Yousef Iskander and Prabhat Mishra, Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution, IEEE International Test Conference (ITC), Phoenix, Arizona, USA, October 28 - November 2, 2018.
C97 Aisharjya Sarkar, Prabhat Mishra and Tamer Kahveci, Identifying Temporal Variation of Transcription in Populations, International Conference on Bioinformatics and Computational Biology (BICOB), pages -, Las Vegas, March 19 - 21, 2018.
C96 Alif Ahmed, Farimah Farahmandi and Prabhat Mishra, Directed Test Generation using Concolic Testing of RTL Models, Design Automation and Test in Europe (DATE), pages 1538-1543, Dresden, Germany, March 19 - 23, 2018.
C95 Jonathan Cruz, Yuanwen Huang, Prabhat Mishra and Swarup Bhunia, An Automated Configurable Trojan Insertion Framework for Dynamic Trust Benchmarks, Design Automation and Test in Europe (DATE), pages 1598-1603, Dresden, Germany, March 19 - 23, 2018.
C94 Jonathan Cruz, Farimah Farahmandi, Alif Ahmed and Prabhat Mishra, Hardware Trojan Detection using ATPG and Model Checking, International Conference on VLSI Design, pages 91-96, Pune, India, January 6-10, 2018.
C93 Farimah Farahmandi and Prabhat Mishra, FSM Anomaly Detection using Formal Analysis, IEEE International Conference on Computer Design (ICCD), pages 313-320, Boston, Massachusetts, November 5 - 8, 2017.
C92 Farimah Farahmandi and Prabhat Mishra, Automated Debugging of Arithmetic Circuits using Incremental Gröbner Basis Reduction, IEEE International Conference on Computer Design (ICCD), pages 193-200, Boston, Massachusetts, November 5 - 8, 2017.
C91 Alif Ahmed and Prabhat Mishra, QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models, IEEE International Conference on Computer Design (ICCD), pages 185-192, Boston, Massachusetts, November 5 - 8, 2017.
C90 Yuanwen Huang and Prabhat Mishra, Vulnerability-aware Energy Optimization using Cache Reconfiguration and Partitioning in Multicore Systems, IEEE International Conference on Computer Design (ICCD), pages 241-248, Boston, Massachusetts, November 5 - 8, 2017.
C89 Kamran Rahmani and Prabhat Mishra, Feature-based Signal Selection for Post-silicon Debug using Machine Learning, IEEE International Conference on Computer Design (ICCD), pages -, Boston, Massachusetts, November 5 - 8, 2017.
C88 Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo and Prabhat Mishra, Cost-Effective Analysis of Post-Silicon Functional Coverage Events, Design Automation and Test in Europe (DATE), pages 392-397, Lausanne, Switzerland, March 27 - 31, 2017.
C87 Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Trojan Localization using Symbolic Algebra, Asia and South Pacific Design Automation Conference (ASPDAC), pages 591-597, Tokyo, Japan, January 16 - 19, 2017. Nominated for Best Paper Award
C86 Yuanwen Huang, Swarup Bhunia and Prabhat Mishra, MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection, ACM Conference on Computer and Communications Security (CCS), pages 130-141, Vienna, Austria, October 24 - 28, 2016.
C85 Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra and Yier Jin, Scalable SoC Trust Verification using Integrated Theorem Proving and Model Checking, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 124-129, McLean, Virginia, May 3 - 5, 2016.
C84 Farimah Farahmandi and Prabhat Mishra, Automated Test Generation for Debugging Arithmetic Circuits, Design Automation and Test in Europe (DATE), pages 1351 - 1356, Dresden, Germany, March 14 - 18, 2016.
C83 Farimah Farahmandi, Prabhat Mishra and Sandip Ray, Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation, Design Automation and Test in Europe (DATE), pages 1477-1480, Dresden, Germany, March 14 - 18, 2016.
C82 Yuanwen Huang and Prabhat Mishra, Reliability and Energy-aware Cache Reconfiguration for Embedded Systems, IEEE International Symposium on Quality Electronic Design (ISQED), pages 313-318, Santa Clara, California, March 15-16, 2016. Best Paper Award
C81 Sudhi Proch and Prabhat Mishra, Test Generation for Hybrid Systems using Clustering and Learning Techniques, International Conference on VLSI Design, pages 589-590, Kolkata, India, January 4-8, 2016.
C80 X. Guo, R. Dutta, P. Mishra and Y. Jin, Automatic RTL-to-Formal Code Converter for IP Security Formal Verification, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages , Austin, Texas, December 12-13, 2016.
C79 Yuanwen Huang, Anupam Chattopadhyay and Prabhat Mishra, Trace Buffer Attack: Security versus Observability Study in Post-Silicon Debug, IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pages 355-360, Daejeon, Korea, October 5-7, 2015.
C78 Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi and Prabhat Mishra, Pre-Silicon Security Verification and Validation: A Formal Perspective, ACM/IEEE Design Automation Conference (DAC), pages 145:1-145:6, 2015.
C77 Zhe Wang, Sanjay Ranka and Prabhat Mishra, Efficient Task Partitioning and Scheduling for Thermal Management in Multicore Processors, IEEE International Symposium on Quality Electronic Design (ISQED), pages -, Santa Clara, California, March 2-4, 2015.
C76 Mingsong Chen, Daian Yue, Xiaoke Qin, Xin Fu and Prabhat Mishra, Variation-Aware Evaluation of MPSoC Task Allocation and Scheduling Strategies using Statistical Model Checking, Design Automation and Test in Europe (DATE), pages 199 - 204, Grenoble, France, March 9 - 13, 2015.
C75 Hadi Hajimiri, Kamran Rahmani and Prabhat Mishra, Efficient Peak Power Estimation using Probabilistic Cost-Benefit Analysis, International Conference on VLSI Design, pages 369-374, Bengaluru, India, January 3-7, 2015.
C74 Prateek Thakyal and Prabhat Mishra, Layout-aware Selection of Trace Signals for Post-Silicon Debug, IEEE International Symposium on VLSI (ISVLSI), pages 326-331, 2014.
C73 Prateek Thakyal and Prabhat Mishra, Layout-aware Signal Selection for Reconfigurable Architectures, International Symposium on VLSI Design and Test (VDAT), pages 1-6, 2014.
C72 Sudhi Proch and Prabhat Mishra, Directed Test Generation for Hybrid Systems, IEEE International Symposium on Quality Electronic Design (ISQED), pages 156-162, Santa Clara, California, March 10-12, 2014.
C71 Kamran Rahmani, Prabhat Mishra and Sandip Ray, Efficient Trace Signal Selection using Augmentation and ILP Techniques, IEEE International Symposium on Quality Electronic Design (ISQED), pages 148-155, Santa Clara, California, March 10-12, 2014.
C70 Xiaoke Qin and Prabhat Mishra, TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems, International Conference on VLSI Design, pages 216-221, Mumbai, India, January 7-9, 2014.
C69 Xiaoke Qin and Prabhat Mishra, Scalable Test Generation by Interleaving Concrete and Symbolic Execution, International Conference on VLSI Design, pages 104-109, Mumbai, India, January 7-9, 2014.
C68 Kamran Rahmani, Prabhat Mishra and Sandip Ray, Scalable Trace Signal Selection using Machine Learning, IEEE International Conference on Computer Design (ICCD), pages 384-389, Asheville, North Carolina, October 6-9, 2013.
C67 Hadi Hajimiri, Mimonah Al Qathrady and Prabhat Mishra, Proactive Thermal Management Using Memory Based Computing, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pages 110-115, New York, July 15-17, 2013. Nominated for Best Paper Award
C66 Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia, Branden Long, Yibo Li and Rashmi Jha, Content-aware Encoding for Improving Energy Efficiency in Multi-Level Cell Resistive Random Access Memory, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pages 76-81, New York, July 15-17, 2013.
C65 Mingsong Chen, Saijie Huang, Geguang Pu and Prabhat Mishra, Branch-and-Bound Style Resource Constrained Scheduling using Efficient Structure-Aware Pruning, IEEE International Symposium on VLSI (ISVLSI), pages 224-229, Natal, Brazil, August 5-7, 2013.
C64 Mingsong Chen and Prabhat Mishra, Assertion-Based Functional Consistency Checking between TLM and RTL Models, International Conference on VLSI Design, pages 320-325, Pune, India, January 5-10, 2013. Nominated for Best Paper Award
C63 Kanad Basu, Prabhat Mishra and Priyadarsan Patra, Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults, International Conference on VLSI Design, pages 291-296, Pune, India, January 5-10, 2013.
C62 Kamran Rahmani and Prabhat Mishra, Efficient Signal Selection using Fine-grained Combination of Scan and Trace Buffers, International Conference on VLSI Design, pages 308-313, Pune, India, January 5-10, 2013.
C61 Hadi Hajimiri, Prabhat Mishra and Swarup Bhunia, Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures, International Conference on VLSI Design, pages 49-54, Pune, India, January 5-10, 2013.
C60 Kanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir and Allon Adir, Dynamic Selection of Trace Signals for Post-Silicon Debug, IEEE International Workshop on Microprocessor Test and Verification(MTV), pages 62-67, Austin, Texas, December 11-13, 2013.
C59 Kanad Basu, Prabhat Mishra and Priyadarsan Patra, Constrained Signal Selection for Post-Silicon Validation, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 71-75, Huntington Beach, California, November 9-10, 2012.
C58 Kamran Rahmani, Hadi Hajimiri, Kartik Shrivastava and Prabhat Mishra, Synergistic Integration of Code Encryption and Compression in Embedded Systems, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 363- 368, Salt Lake City, USA, May 3-4, 2012.
C57 Kamran Rahmani, Prabhat Mishra and Swarup Bhunia, Memory-based Computing for Performance and Energy Improvement in Multicore Architectures, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 287-290, Salt Lake City, USA, May 3-4, 2012.
C56 Xiaoke Qin and Prabhat Mishra, Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols, Design Automation and Test in Europe (DATE), pages 3-8, Dresden, Germany, March 12 - 16, 2012. Nominated for Best Paper Award
C55 Hadi Hajimiri and Prabhat Mishra, Intra-task Dynamic Cache Reconfiguration, International Conference on VLSI Design, pages 430-435, Hyderabad, India, January 9-11, 2012.
C54 Zhe Wang, Sanjay Ranka and Prabhat Mishra, Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems, International Conference on VLSI Design, pages 161-166, Hyderabad, India, January 9-11, 2012.
C53 Kanad Basu, Prabhat Mishra and Priyadarsan Patra, Efficient Combination of Trace and Scan Signals for Post Silicon Validation and Debug, IEEE International Test Conference (ITC), pages 1-8 , Anaheim, California, USA, September 18-23, 2011.
C52 Weixun Wang, Prabhat Mishra and Sanjay Ranka, Dynamic Cache Reconfiguration and Partitioning for Energy Optimization in Real-Time Multi-Core Systems, ACM/IEEE Design Automation Conference (DAC), pages 948-953, 2011.
C51 Hadi Hajimiri, Kamran Rahmani, and Prabhat Mishra, Synergistic Integration of Dynamic Cache Reconfiguration and Code Compression in Embedded Systems, International Green Computing Conference (IGCC), pages 1-8, Orlando, Florida, July 25-28, 2011.
C50 Hadi Hajimiri, Somnath Paul, Anandaroop Ghosh, Swarup Bhunia and Prabhat Mishra, Reliability Improvement in Multicore Architectures Through Computing in Embedded Memory, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pages , Seoul, Korea, August 7-10, 2011.
C49 Xiaoke Qin and Prabhat Mishra, Efficient Directed Test Generation for Validation of Multicore Architectures, International Symposium on Quality Electronic Design (ISQED), pages 276-283, Santa Clara, California, March 14-16, 2011.
C48 Kanad Basu and Prabhat Mishra, Efficient Trace Data Compression using Statically Selected Dictionary, IEEE VLSI Test Symposium (VTS), pages 14-19, Dana Point, California, May 1-5, 2011.
C47 Mingsong Chen and Prabhat Mishra, Decision Ordering Based Property Decomposition for Functional Test Generation, Design Automation and Test in Europe (DATE), pages 167-172, Grenoble, France, March 14 - 18, 2011.
C46 Kanad Basu and Prabhat Mishra, Efficient Trace Signal Selection for Post Silicon Validation and Debug, International Conference on VLSI Design, pages 352-357, Chennai, India, January 2-7, 2011. Best Paper Award
C45 Kartik Shrivastava and Prabhat Mishra, Dual Code Compression for Embedded Systems, International Conference on VLSI Design, pages 177-182, Chennai, India, January 2-7, 2011.
C44 Weixun Wang, Sanjay Ranka and Prabhat Mishra, A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems, International Conference on VLSI Design, pages 334-339, Chennai, India, January 2-7, 2011.
C43 Weixun Wang and Prabhat Mishra, Pre-DVS: Preemptive Dynamic Voltage Scaling for Real-Time Systems with Approximation Scheme, ACM/IEEE Design Automation Conference (DAC), pages 705 - 710, Anaheim, California, USA, June 13-18, 2010.
C42 Weixun Wang, Xiaoke Qin and Prabhat Mishra, Temperature- and Energy-Constrained Scheduling in Multitasking Systems: A Model Checking Approach, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 85 - 90, Austin, Texas, USA, August 18-20, 2010.
C41 Mingsong Chen, Xiaoke Qin and Prabhat Mishra, Efficient Decision Ordering Techniques for SAT-based Test Generation, Design Automation and Test in Europe (DATE), pages 490-495, Dresden, Germany, March 8 - 12, 2010.
C40 Xiaoke Qin, Mingsong Chen and Prabhat Mishra, Synchronized Generation of Directed Tests using Satisfiability Solving, International Conference on VLSI Design, pages 351-356, Bangalore, India, January 3-7, 2010.
C39 Weixun Wang and Prabhat Mishra, Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems, International Conference on VLSI Design, pages 357-362, Bangalore, India, January 3-7, 2010.
C38 Nga Dang, Abhik Roychoudhury, Tulika Mitra and Prabhat Mishra, Generating Test Programs to Cover Pipeline Interactions, ACM/IEEE Design Automation Conference (DAC), pages 142-147, San Francisco, California, USA, July 26-31, 2009. Nominated for Best Paper Award
C37 Weixun Wang and Prabhat Mishra, Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems, IEEE International Symposium on VLSI (ISVLSI), pages 145-150, Tampa, Florida, USA, May 13-15, 2009.
C36 Chetan Murthy and Prabhat Mishra, Lossless Compression using Efficient Encoding of Bitmasks, IEEE International Symposium on VLSI (ISVLSI), pages 163-168, Tampa, Florida, USA, May 13-15, 2009.
C35 Chetan Murthy and Prabhat Mishra, Bitmask-based Control Word Compression for NISC Architectures, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 321-326, Boston, USA, May 10-12, 2009.
C34 Xiaoke Qin and Prabhat Mishra, Efficient Placement of Compressed Code for Parallel Decompression, International Conference on VLSI Design, pages 335-340, New Delhi, India, January 5-9, 2009.
C33 Weixun Wang, Prabhat Mishra and Ann-Gordon Ross, SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems, International Conference on VLSI Design, pages 547-552, New Delhi, India, January 5-9, 2009.
C32 Prabhat Mishra and Mingsong Chen, Efficient Techniques for Directed Test Generation using Incremental Satisfiability, International Conference on VLSI Design, pages 65-70, New Delhi, India, January 5-9, 2009. Nominated for Best Paper Award
C31 Heon-Mo Koo and Prabhat Mishra, Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 137-142, Atlanta, USA, October 19 - 24, 2008.
C30 Kanad Basu and Prabhat Mishra, A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 83-88, Orlando, USA, May 4 - 6, 2008.
C29 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Coverage-driven Automatic Test Generation for UML Activity Diagrams, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 139-142, Orlando, USA, May 4 - 6, 2008.
C28 Seok-Won Seong and Prabhat Mishra, An Efficient Code Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, Design Automation and Test in Europe (DATE), pages 582-587, Nice, France, April 16 - 20, 2007.
C27 Heon-Mo Koo and Prabhat Mishra, Automated Micro-architectural Test Generation for Validation of Modern Processors, US-Korea Conference on Global Challenges in Science and Technology (UKC), Washington DC, August 9-12, 2007.
C26 Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra and Xu Cheng, A Retargetable Software Timing Analyzer Using Architecture Description Language, Asia and South Pacific Design Automation Conference (ASPDAC), pages 396-401, Yokohama, Japan, January 23 - 26, 2007.
C25 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Towards RTL Test Generation from SystemC TLM Specifications, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 91-96, Irvine, California, November 7-9, 2007.
C24 Seok-Won Seong and Prabhat Mishra, A Bitmask-based Code Compression Technique for Embedded Systems, IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 251-254, San Jose, California, November 5 - 9, 2006.
C23 Heon-Mo Koo and Prabhat Mishra, Test Generation using SAT-based Bounded Model Checking for Validation of Pipelined Processor, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 362-365, Philadelphia, USA, April 30 - May 2, 2006.
C22 Heon-Mo Koo and Prabhat Mishra, Coverage-driven Functional Test Generation for Processor Validation using Formal Methods, US-Korea Conference on Science, Technology, and Entrepreneurship (UKC), New Jersey, August 10-13, 2006.
C21 Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Property Decompositions for Validation of Pipelined Processors, Design Automation and Test in Europe (DATE), pages 1240-1245, Munich, Germany, March 6-10, 2006.
C20 Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra and Magdy Abadir, Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 33-36, Austin, Texas, USA, December 4-5, 2006.
C19 Prabhat Mishra, Heon-Mo Koo, and Zhuo Huang, Language-driven Validation of Pipelined Processors using Satisfiability Solvers, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 119-126, Austin, Texas, USA, November 3-4, 2005.
C18 Mehrdad Reshadi and Prabhat Mishra, Memory Access Optimizations in Instruction-Set Simulators, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 237-242, New York, September 19-21, 2005.
C17 Prabhat Mishra and Nikil Dutt, Functional Coverage Driven Test Generation for Validation of Pipelined Processors, Design Automation and Test in Europe (DATE), pages 678-683, Munich, Germany, March 7-11, 2005.
C16 Prabhat Mishra and Nikil Dutt, Functional Validation of Programmable Architectures, EUROMICRO Symposium on Digital System Design (DSD), pages 12-19, Rennes, France, August 31 - September 3, 2004. Keynote Paper
C15 Prabhat Mishra and Nikil Dutt, Graph-based Functional Test Program Generation for Pipelined Processors, Design Automation and Test in Europe (DATE), pages 182-187, Paris, France, February 16-20, 2004.
C14 Prabhat Mishra, Arun Kejariwal, and Nikil Dutt, Synthesis-driven Exploration of Pipelined Embedded Processors, International Conference on VLSI Design, pages 921-926, Mumbai, India, January 5-9, 2004.
C13 Prabhat Mishra, Nikil Dutt, and Yaron Kashai, Functional Verification of Pipelined Processors: A Case Study, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 79-84, Austin, USA, September 9-10, 2004.
C12 Mehrdad Reshadi, Prabhat Mishra, and Nikil Dutt, Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation, Design Automation Conference (DAC), pages 758-763, Anaheim, USA, June 2-6, 2003.
C11 Prabhat Mishra, Arun Kejariwal and Nikil Dutt, Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models, IEEE International Workshop on Rapid System Prototyping (RSP), pages 226-232, San Diego, USA, June 9-11, 2003.
C10 Prabhat Mishra and Nikil Dutt, A Methodology for Validation of Microprocessors using Equivalence Checking, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 83-88, Austin, USA, May 29-30, 2003.
C9 Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, and Nikil Dutt, An Efficient Retargetable Framework for Instruction-Set Simulation, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 13-18, California, USA, October 1-3, 2003. Best Paper Award
C8 Prabhat Mishra, Hiroyuki Tomiyama, Nikil Dutt, and Alex Nicolau, Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units, Design Automation and Test in Europe (DATE), pages 36-43, Paris, France, March 4-8, 2002.
C7 Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil Dutt, and Alex Nicolau, Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language, Asia and South Pacific Design Automation Conference (ASPDAC) & VLSI Design, pages 458-463, Bangalore, India, January 7-11, 2002.
C6 Prabhat Mishra and Nikil Dutt, Automatic Functional Test Program Generation for Pipelined Processors using Model Checking, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 99-103, Cannes, France, October 27-29, 2002.
C5 Prabhat Mishra, Narayanan Krishnamurthy, Nikil Dutt and Magdy Abadir, A Property Checking Approach to Microprocessor Verification using Symbolic Simulation, Microprocessor Test and Verification (MTV), Austin, Texas, June 6-7, 2002.
C4 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Automatic Validation of Pipeline Specifications, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 9-13, Monterey, California, November 7-9, 2001.
C3 Prabhat Mishra, Frederic Rousseau, Nikil Dutt, and Alex Nicolau, Architecture Description Language driven Design Space Exploration in the Presence of Coprocessors, Synthesis And System Integration of MIxed Technologies (SASIMI), Nara, Japan, October 18-19, 2001.
C2 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Functional Abstraction driven Design Space Exploration of Heterogeneous Programmable Architectures, International Symposium on System Synthesis (ISSS), Montreal, Canada, October 1-3, pages 256-261, 2001.
C1 Prabhat Mishra, Peter Grun, Nikil Dutt, and Alex Nicolau, Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language, International Conference on VLSI Design, pages 70-75, Bangalore, India, January 3-7, 2001.

Ph.D. Dissertations

D14 Hasini Witharana, Design of Trustworthy Systems using Security Assertions, Ph.D. Dissertation, University of Florida, June 6, 2024.
D13 Daniel Volya, Steering Quantum Computers as Open Quantum Systems, Ph.D. Dissertation, University of Florida, May 31, 2024.
D12 Zhixin Pan, Securing Computer Systems against Malicious Attacks using Machine Learning, Ph.D. Dissertation, University of Florida, December 2022. EDAA Outstanding Dissertation Award 2004
D11 Subodha Charles, Design of Secure and Trustworthy Network-on-Chip Architectures, Ph.D. Dissertation, University of Florida, December 2020.
D10 Yangdi Lyu, Test Generation for System-on-Chip Security Validation, Ph.D. Dissertation, University of Florida, April 2020.
D9 Farimah Farahmandi, Formal Verification of Hardware Security and Trust, Ph.D. Dissertation, University of Florida, May 2018.
D8 Yuanwen Huang, System-on-Chip Vulnerability Analysis and Mitigation Techniques, Ph.D. Dissertation, University of Florida, June 2017.
D7 Kamran Rahmani, Scalable Signal Selection for Post-Silicon Debug, Ph.D. Dissertation, University of Florida, April 2017.
D6 Kanad Basu, Efficient Observability Enhancement Techniques for Post-Silicon Validation and Debug, Ph.D. Dissertation, University of Florida, August 2012.
D5 Xiaoke Qin, System-Level Validation of Multicore Architectures, Ph.D. Dissertation, University of Florida, April 2012.
D4 Weixun Wang, Energy-Aware Scheduling and Dynamic Reconfiguration in Real-Time Embedded Systems, Ph.D. Dissertation, University of Florida, August 2011.
D3 Mingsong Chen, Efficient Approaches for Functional Validation of SoC Designs using High-Level Specifications, Ph.D. Dissertation, University of Florida, August 2010.
D2 Heon-Mo Koo, Coverage-driven Test Generation for Functional Validation of Pipelined Processors, Ph.D. Dissertation, University of Florida, December 2008.
D1 Prabhat Mishra, Specification-driven Validation of Programmable Embedded Systems, Ph.D. Dissertation, University of California, Irvine, March 2004. EDAA Outstanding Dissertation Award 2004.

M.S. Theses

T6 Sudhi Proch, Directed Test Generation for Hybrid Systems, MS Thesis, University of Florida, May 2014.
T5 Prateek Thakyal, Layout-aware Signal Selection for Post-Silicon Debug, MS Thesis, University of Florida, May 2014.
T4 Kartik Shrivastava, Synergistic Integration of Code Compression and Encryption in Embedded Systems, MS Thesis, University of Florida, August 2010.
T3 Chetan Murthy, Decoding-Aware Compression Techniques for Reconfigurable Systems, MS Thesis, University of Florida, December 2008.
T2 Seok-Won Seong, Dictionary-based Code Compression Techniques using Bitmasks for Embedded Systems, MS Thesis, University of Florida, April 2006.
T1 Prabhat Mishra, Illumination Modeling with Reflections, M.Tech. Thesis, Indian Institute of Technology, Kharagpur, January 1996.

Undergraduate (Honors) Theses

U5 Miranda Overstreet, Robustness Metrics for Evasion Attacks on Neural Networks, Honors Thesis, University of Florida, April 2020.
U4 Jennifer Sheldon, Malware Detection Using Hardware Trace Analysis, Honors Thesis, University of Florida, April 2020.
U3 Jonathan Cruz, Hardware Trojan Detection using ATPG and Model Checking, Honors Thesis, University of Florida, April 2017.
U2 David Nash, Use of Similarity in Dictionary Selection for Bitmask-based Code Compression, Honors Thesis, University of Florida, April 2007.
U1 Prabhat Mishra, Natural Language Query Interface to a Database, B.E. Thesis, Jadavpur University, April 1994.

Patents and Copyrights

P30 Prabhat Mishra, Sahan Sanjaya and Daniel Volya, Measurement-Induced Steering of Variational Quantum Algorithms, U.S. Provisional Patent Application No. 63/665,472, filed June 28, 2024.
P29 Prabhat Mishra, Daniel Volya and Andrey Nikitin, Fast Quantum Characterization via Riemannian Optimization, U.S. Provisional Patent Application No. 63/660,665, filed June 17, 2024.
P28 Prabhat Mishra and Daniel Volya, Quantum Benchmarking via Random Dynamical Quantum Maps, U.S. Provisional Patent Application No. 63/656,384, filed June 5, 2024.
P27 Prabhat Mishra and Hansika Weerasena, System and Method for Performing Multicast Authentication in Network-on-Chip Systems, U.S. Provisional Patent Application No. 63/573,708, filed April 3, 2024.
P26 Prabhat Mishra, Daniel Volya and Hasini Witharana, Quantum Device Testing using Concurrent Assertions, U.S. Provisional Patent Application No. 63/619,368, filed January 10, 2024.
P25 Prabhat Mishra and Daniel Volya, Logical Qubit State Preparation using Quantum Steering, U.S. Provisional Patent Application No. 63/609,493, filed December 13, 2023.
P24 Prabhat Mishra, Zhixin Pan, and Daniel Volya, Qubit State Preparation using Quantum Steering, U.S. Provisional Patent Application No. 63/617,974, filed January 5, 2024.
P23 Prabhat Mishra and Aruna Jayasena, Scalable Detection of Hardware Trojans using ATPG-based Activation of Rare Events, U.S. Non-Provisional Patent Application No. 18/794,774, filed August 5, 2024.
P22 Prabhat Mishra, Emma Andrews, Aruna Jayasena, Test Vector Leakage Assesment of Asymmetric Cryptography Algorithms, U.S. Non-Provisional Patent Application No. 18/667,408, filed May 17, 2024.
P21 Prabhat Mishra, Hasini Witharana and Sahan Sanjaya, Dynamic Refinement of Hardware Assertion Checkers, U.S. Non-Provisional Patent Application No. 18/595,698, filed March 5, 2024.
P20 Prabhat Mishra, Daniel Volya and Zachery Utt, Quantum Measurement Discrimination using Distribution Functions, U.S. Non-Provisional Patent Application Serial No. 18/439,968, filed February 13, 2024.
P19 Prabhat Mishra and Zhixin Pan, Hardware Trojan Detection using Shapley Ensemble Boosting, U.S. Provisional Patent Application Serial No. 18/437,674, filed February 9, 2024.
P18 Prabhat Mishra and Zhixin Pan, Hardware Acceleration of Explainable Machine Learning, U.S. Non-Provisional Patent Application No. 18/178,945, filed March 6, 2023.
P17 Prabhat Mishra and Zhixin Pan, AI-based Trojans for Evading Machine Learning-based Detection, U.S. Non-Provisional Patent Application No. 18/174,342, filed February 24, 2023.
P16 Prabhat Mishra, Hansika Weerasena and Subodha Charles, Securing On-Chip Communication using Chaffing and Winnowing with All-or-Nothing Transform, U.S. Provisional Patent Application Serial No. 63/275,552, filed November 4, 2021.
P15 Prabhat Mishra and Zhixin Pan, Automated Cyberattack Detection using Time-Sequential Data, Explainable Machine Learning, and/or Ensemble Boosting Frameworks, U.S. Provisional Patent Application Serial No. 18/045,563, filed October 11, 2022.
P14 Prabhat Mishra and Zhixin Pan, Hardware Trojan Detection using Reinforcement Learning, U.S. Patent No. 12,079,334, September 3, 2024.
P13 Prabhat Mishra, Zhixin Pan and Jennifer Sheldon, Hardware Trojan Detection Using Path Delay Based Side-Channel Analysis and Reinforcement Learning, U.S. Patent No. 11,775,693, October 3, 2023.
P12 Prabhat Mishra, Zhixin Pan and Jennifer Sheldon, Hardware-Assisted Malware Detection using Explainable Machine Learning, U.S. Patent No. 11,829,475, November 28, 2023.
P11 Prabhat Mishra, Subodha Charles and Vincent Bindschaedler, Securing On-Chip Communication using Digital Watermarking, U.S. Non-Provisional Patent Application Serial No. 17/525,176, filed November 12, 2021.
P10 Prabhat Mishra and Yangdi Lyu, Delay-based Side-channel Analysis for Trojan Detection, U.S. Patent No. 11,580,265, February 14, 2023.
P9 Prabhat Mishra and Subodha Charles, Reconfigurable Network-on-Chip Security Architecture, U.S. Utility Patent No. 11,593,298, February 28, 2023.
P8 Subodha Charles and Prabhat Mishra, Lightweight and Trust-aware Routing in NoC based SoC Architectures, U.S. Patent No. 11,770,399, September 26, 2023.
P7 Prabhat Mishra, Subodha Charles and Yangdi Lyu, Securing System-on-Chip using Incremental Cryptography, U.S. Patent No. 11,552,782, January 10, 2023.
P6 Prabhat Mishra, Subodha Charles and Yangdi Lyu, Real-Time Detection and Localization of DoS Attacks in NoC based SoC Architectures, U.S. Patent No. 11,797,667, October 24, 2023.
P5 Prabhat Mishra and Yangdi Lyu, Maximization of Side-Channel Sensitivity for Trojan Detection, U.S. Patent No. 11,579,185, February 14, 2023.
P4 Prabhat Mishra and Yangdi Lyu, Trigger Activation by Repeated Maximal Clique Sampling, U.S. Patent No. 11,568,046, January 31, 2023.
P3 Prabhat Mishra, Swarup Bhunia and Yuanwen Huang, MERS: Statistical Test Generation for Side-Channel Analysis Based Trojan Detection, U.S. Copyright Registration TXu 2-112-970, August 17, 2018.
P2 Swarup Bhunia, Prabhat Mishra and Jonathan Cruz, Trojan Insertion Tool, US Patent 11,144,648, October 12, 2021.
P1 Prabhat Mishra and Nikil Dutt, Functional Coverage driven Test Generation for Validation of Pipelined Processors, US Patent 7533294, May 12, 2009.

Book Chapters

BC35 Prabhat Mishra and Subodha Charles, Trustworthy System-on-Chip Design using Secure On-Chip Communication Architectures, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC34 Subodha Charles and Prabhat Mishra, Lightweight Encryption using Incremental Cryptography, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC33 Subodha Charles and Prabhat Mishra, Trust-aware Routing in Network-on-Chip Architectures, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC32 Subodha Charles and Prabhat Mishra, Lightweight Anonymous Routing for On-Chip Interconnects, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC31 Subodha Charles and Prabhat Mishra, Real-time Detection and Localization of Denial-of-Service Attacks, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC30 Subodha Charles and Prabhat Mishra, Securing On-Chip Communication using Digital Watermarking, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC29 Chamika Sudusinghe, Subodha Charles and Prabhat Mishra, Network-on-Chip Attack Detection using Machine Learning, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC28 Manju Rajan, Abhijit Das, John Jose and Prabhat Mishra, Trojan-Aware Network-on-Chip Routing, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC27 Aruna Jayasena, Subodha Charles and Prabhat Mishra, Network-on-Chip Security and Trust Verification, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC26 Prabhat Mishra and Subodha Charles, The Future of Secure and Trustworthy Network-on-Chip Architectures, Network-on-Chip Security and Privacy, P. Mishra and S. Charles (editors), Springer, 2021.
BC25 Alif Ahmed, Farimah Farahmandi, Yousef Iskander and Prabhat Mishra, Security and Trust Verification of IoT SoCs, Security and Fault Tolerance in Internet of Things, R. Chakraborty, J. Mathew and A. Vasilakos (editors), Springer, 2018.
BC24 Alif Ahmed, Kamran Rahmani and Prabhat Mishra, Post-Silicon Signal Selection using Machine Learning, Post-Silicon Validation and Debug, P. Mishra and F. Farahmandi (editors), Springer, 2018.
BC23 Farimah Farahmandi and Prabhat Mishra, Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis, Post-Silicon Validation and Debug, P. Mishra and F. Farahmandi (editors), Springer, 2018.
BC22 Farimah Farahmandi and Prabhat Mishra, Observability-aware Directed Test Generation, Post-Silicon Validation and Debug, P. Mishra and F. Farahmandi (editors), Springer, 2018.
BC21 Subodha Charles and Prabhat Mishra, Network-on-Chip Validation and Debug, Post-Silicon Validation and Debug, P. Mishra and F. Farahmandi (editors), Springer, 2018.
BC20 Yangdi Lyu, Yuanwen Huang and Prabhat Mishra, SoC Security versus Post-Silicon Debug Conflict, Post-Silicon Validation and Debug, P. Mishra and F. Farahmandi (editors), Springer, 2018.
BC19 Farimah Farahmandi and Prabhat Mishra, Post-Silicon SoC Validation Challenges, Post-Silicon Validation and Debug, P. Mishra and F. Farahmandi (editors), Springer, 2018.
BC18 Farimah Farahmandi and Prabhat Mishra, The Future of Post-Silicon Debug, Post-Silicon Validation and Debug, P. Mishra and F. Farahmandi (editors), Springer, 2018.
BC17 Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Formal Approaches to Hardware Trust Verification, The Hardware Trojan War: Attacks, Myths, and Defenses, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC16 Prabhat Mishra, Mark Tehranipoor and Swarup Bhunia, Security and Trust Vulnerabilities in Third-party IPs, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC15 Prabhat Mishra, Swarup Bhunia and Mark Tehranipoor, The Future of Trustworthy SoC Design, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC14 Yuanwen Huang and Prabhat Mishra, Test Generation for Detection of Malicious Parametric Variations, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC13 Farimah Farahmandi and Prabhat Mishra, Validation of IP Security and Trust, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC12 Anupam Chattopadhyay, Nikil Dutt, Rainer Leupers and Prabhat Mishra, Processor Modeling and Design Tools, Electronic Design Automation for Integrated Circuits Handbook (Second Edition), L. Lavagno, I. Markov, G. Martin and L. Scheffer (Editors), CRC Press, 2016.
BC11 Sandip Ray, Swarup Bhunia and Prabhat Mishra, Security Validation in System-on-Chip, Fundamentals of IP and SoC Security - Design, Verification and Debug, S. Bhunia, S. Ray and S. Sur-Kolay (editors), Springer, 2016.
BC10 Prabhat Mishra, Computer Architecture, Encyclopedia of Life Support Systems (EOLSS), United Nations Educational, Scientific and Cultural Organization (UNESCO), 2012.
BC9 Weixun Wang, Xiaoke Qin and Prabhat Mishra, Energy-Aware Dynamic Cache Reconfigurations and Voltage Scaling in Real-Time Systems, Handbook of Energy-Aware and Green Computing, I. Ahmad and S. Ranka, Editors, Chapman & Hall/CRC Press, pages 543-572, 2011.
BC8 Nirmalya Bandyopadhyay, Kanad Basu and Prabhat Mishra, HMDES, ISDL and Other Contemporary ADLs, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC7 Prabhat Mishra and Nikil Dutt, EXPRESSION: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC6 Prabhat Mishra and Aviral Shrivastava, ADL-driven Methodologies for Design Automation of Embedded Processors, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC5 Prabhat Mishra and Nikil Dutt, Introduction to Architecture Descripton Languages, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC4 Prabhat Mishra and Nikil Dutt, Architecture Description Languages, Customizable and Configurable Embedded Processors, Paolo Ienne and Rainer Leupers, Editors, Morgan Kaufmann Publishers, 2006.
BC3 Prabhat Mishra and Nikil Dutt, Processor Modeling and Design Tools, The EDA Handbook, L. Scheffer, L. Lavagno and G. Martin (Editors), CRC Press, 2006.
BC2 Prabhat Mishra and Nikil Dutt, Architecture Description Languages for Programmable Embedded Systems, System On Chip: Next Generation Electronics, Bashir M. Al-Hashimi, Editor, IEE Press, 2005.
BC1 Prabhat Mishra and Nikil Dutt, Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions, in Design and Analysis of Distributed Embedded Systems, Bernd Kleinjohann et al., Editors, Kluwer Academic Publishers, 2002, pp. 81-90.

Keynotes

K7 Prabhat Mishra, Design Automation for Quantum Computing, International Workshop on Design Automation for Quantum Computing, IEEE Communications Society, Guwahati, India, July 1, 2024.
K6 Prabhat Mishra, Securing Hardware for Designing Trustworthy Systems, International Conference on Contemporary Computing (IC3), Noida, India, August 5, 2022.
K5 Prabhat Mishra, Securing Hardware for Designing Trustworthy Systems, ISEA International Conference on Security and Privacy (ISEA-ISAP), Guwahati, India, February 29, 2020.
K4 Prabhat Mishra, Securing Hardware for Designing Trustworthy Systems, Brazilian Symposium on Information and Computational Systems Security (SBSEG), São Paulo, Brazil, September 3, 2019.
K3 Prabhat Mishra, Securing Hardware for Designing Trustworthy Systems, SPARC Workshop on Hardware Security (HSW), New Delhi, India, July 27, 2019.
K2 Prabhat Mishra, System-on-Chip Design using Potentially Untrusted Third-Party IPs, ISEA Workshop on Advances in Hardware Security (AHS), Guwahati, India, May 24, 2019.
K1 Prabhat Mishra, Cruising the Landscape of System Validation: Dangers and Opportunities, International Symposium on VLSI Design and Test (VDAT), Coimbatore, July 18, 2014.

Panels

P4 Prabhat Mishra, Brian Santo (EETimes), Will Ruby (FortifyIQ), Mike Borza (Synopsys) Trust and Verify: Overcoming costly and piecemeal approaches to pre-silicon side-channel attack vulnerability analysis and verification, ACM/IEEE Design Automation Conference (DAC), San Francisco, December 6, 2021.
P3 Davide Bertozzi (Univ. of Ferrara), Sujay Deb (IIIT Delhi), Azin Ebrahimi (KTH Royal Institute of Technology) and Prabhat Mishra Machine Learnig and Networks on Chip, International Workshop on Network on Chip Architectures (DAC), October 22, 2021.
P2 Prabhat Mishra, CCC Visioning Workshop on Extreme Scale Design Automation (ESDA 2014) organized by CRA Computing Community Consortium (CCC) and ACM SIGDA, Tampa, February 21-22, 2014.
P1 Prabhat Mishra, Sharad Kumar (Freescale), Eric Rentschler (Mentor Graphics), Kevin Reick (IBM), Daniel Sorin ( Duke Univ.), Diagnosing Disaster: Getting to Post-Silicon, ACM/IEEE Design Automation Conference (DAC), San Francisco, June 5, 2014.

Special Sessions

S3 Prabhat Mishra, Huiyang Zhou, Swaroop Ghosh and Samah Saeed, Noise-aware Quantum Synthesis and Compilation IEEE International Conference on Computer Design (ICCD), October 23-26, 2022.
S2 Prabhat Mishra, Susmita Sur-Kolay, Himanshu Thapliyal and Christopher J. Wood, Reliable Quantum Computing using Noisy Intermediate-Scale Quantum Systems, IEEE International Conference on Computer Design (ICCD), October 18-21, 2020.
S1 Prabhat Mishra Towards Trust Validation of Hardware Intellectual Property (IP) Cores, Special session on New Directions in Hardware Security, International Conference on VLSI Design (VLSID), January 5, 2016.

Tutorials

T13 Zhixin Pan and Prabhat Mishra, Explainable AI for Cybersecurity, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, May 6, 2024.
T12 Prabhat Mishra, Hardware Security and Trust Verification, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, May 6, 2024.
T11 Prabhat Mishra and Robert Wille (TU Munich), Design Automation for Quantum Computing, International Conference on VLSI Design, Kolkata, India, January 6-7, 2024.
T10 Daniel Volya and Prabhat Mishra, Quantum Noise Characterization and Mitigation Techniques, IEEE International Conference on Quantum Computing and Engineering (QCE), Bellevue, Washington, September 17-22, 2023.
T9 Prabhat Mishra, Hardware Security and Trust Verification, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, California, May 1, 2023.
T8 Prabhat Mishra, Hardware Security and Trust Verification, Embedded Systems Week (ESWEEK), Shanghai, October 7, 2022.
T7 D. Volya and P. Mishra, Quantum Noise Characterization and Mitigation for NISQ Systems, IEEE International Conference on Quantum Computing and Engineering (QCE), Broomfield, Colorado, September 19, 2022.
T6 Prabhat Mishra and Shobha Vasudevan, Hardware Trust Validation using Machine Learning and Formal Methods, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, June 27, 2022.
T5 Prabhat Mishra, Verification of Hardware IP Security and Trust, IACR Conference on Cryptographic Hardware and Embedded Systems (CHES), Atlanta, USA, August 25, 2019.
T4 Prabhat Mishra and Rajat Subhra Chakraborty (IIT Kharagpur), Hardware Intellectual Property (IP) Security and Trust: Challenges and Solutions, International Conference on VLSI Design, Pune, India, January 7, 2018.
T3 Sharad Kumar (NXP), John Schumann (IBM), Sukhbinder Singh (Intel), Sankaran Menon (Intel), and Prabhat Mishra, The Future of SoC System Validation & Debug. and Why You Should Care!, Design Automation Conference (DAC), Austin, Texas, June 19, 2017.
T2 Prabhat Mishra, Swarup Bhunia (Case Western Reserve University), and Srivaths Ravi (Texas Instruments), Validation and Debug of Security and Trust Issues in Embedded Systems, International Conference on VLSI Design, Bangalore, India, January 4, 2015.
T1 Prabhat Mishra, Masahiro Fujita (Univ. of Tokyo), Virendra Singh (IIT Bombay), Nagesh Tamarapalli (AMD), Sharad Kumar (Freescale) and Rajesh Mittal (TI), Post-Silicon Validation, Debug and Diagnosis, International Conference on VLSI Design, Pune, India, January 6, 2013.

Non-Referred Publications (Guest Editorials, Magazine Articles, Informal Proceedings, ...)

M26 Emma Andrews and Prabhat Mishra, Explainable Metric Learning for Deflating Data Bias, SRC TECHCON, Austin, Texas, September 8-10, 2024.
M25 Laura Chang, Zhixin Pan and Prabhat Mishra, Deflating Data Bias through Guided Diffusion, SRC TECHCON, Austin, Texas, September 10-12, 2023.
M24 Emma Andrews, Zhixin Pan and Prabhat Mishra, Towards Accurate Measurement of Pretraining Bias, SRC TECHCON, Austin, Texas, September 10-12, 2023.
M23 Aruna Jayasena and Prabhat Mishra, Towards Formal Verification of Hardware-Firmware Implementations, SRC TECHCON, Austin, Texas, September 10-12, 2023.
M22 Hasini Witharana and Prabhat Mishra, Scalable Assertion-based Validation of Trusted Execution Environments, SRC TECHCON, Austin, Texas, September 10-12, 2023.
M21 Zhixin Pan and Prabhat Mishra, Hardware-based Acceleration of Explainable AI Models, GOMACTech Conference, San Diego, March 20-23, 2023.
M20 Daniel Volya and Prabhat Mishra, A Quantum Algorithm for Graph Clustering, GOMACTech Conference, San Diego, March 20-23, 2023.
M19 Zachery Utt, Daniel Volya and Prabhat Mishra, Mitigation of Quantum Measurement Errors with Distribution-based Learning, GOMACTech Conference, San Diego, March 20-23, 2023.
M18 Hansika Weerasena and Prabhat Mishra, Preserving Confidentiality and Anonymity in NoC-based SoCs, GOMACTech Conference, San Diego, March 20-23, 2023.
M17 Aruna Jayasena and Prabhat Mishra, Efficient Activation of Stealthy Triggers in Hardware Trojans, GOMACTech Conference, San Diego, March 20-23, 2023.
M16 Khushboo Rani, Emma Andrews, Aruna Jayasena and Prabhat Mishra, Defending Elliptic Curve Cryptography against Laser Fault injection Attacks, GOMACTech Conference, San Diego, March 20-23, 2023.
M15 Hasini Witharana and Prabhat Mishra, Security validation of Trusted Execution Environments, GOMACTech Conference, San Diego, March 20-23, 2023.
M14 Hasini Witharana and Prabhat Mishra, Speculative Load Forwarding Attack on Modern Processors, SRC TECHCON, 2022.
M13 Aruna Jayasena and Prabhat Mishra, Network-on-Chip Trust Validation using Security Assertions, SRC TECHCON, 2022.
M12 Hasini Witharana and Prabhat Mishra, Automated Generation of Security Assertions for RTL Models, SRC TECHCON, 2021.
M11 Hasini Witharana and Prabhat Mishra, Directed Test Generation for Activation of Assertions in RTL Models, SRC TECHCON, 2020.
M10 Prabhat Mishra, Debdeep Mukhopadhyay and Swarup Bhunia Guest Editorial on Machine Intelligence for Security and Privacy Analytics, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019.
M9 Prabhat Mishra, Aviral Shrivastava and Preeti Panda, Guest Editorial on Energy-efficient Computing for Embedded and IoT Devices, IET Computer & Digital Techniques, 2019.
M8 Prabhat Mishra, Towards Trust Validation of Hardware Intellectual Property (IP) Cores, Special session on New Directions in Hardware Security, International Conference on VLSI Design, Kolkata, India, January 4-8, 2016.
M7 Zeljko Zilic, Prabhat Mishra and Sandeep Shukla, Guest Editors' Introduction: Special Section on System-Level Design and Validation of Heterogeneous Chip Multiprocessors, IEEE Transactions on Computers, 62(2), pages 209-210, February 2013.
M6 Prabhat Mishra, Zeljko Zilic and Sandeep Shukla, Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models, IEEE Design & Test of Computers, 28(3), pages 6-9, May-June 2011.
M5 Sandeep Shukla, Prabhat Mishra and Zeljko Zilic, A Brief History of Multiprocessors and EDA, IEEE Design & Test of Computers, 28(3), pages 52-53, May-June 2011.
M4 Zeljko Zilic, Prabhat Mishra and Sandeep Shukla, Challenges of Rapidly Emerging Consumer Space Multiprocessors, IEEE Design & Test of Computers, 28(3), pages 52-53, May-June 2011.
M3 Prabhat Mishra, Guest Editorial, Journal of Electronic Testing, volume 26, number 2, pages 149-150, 2010.
M2 Prabhat Mishra, Guest Editor Introduction: Special Issue on Nano/Bio-Inspired Applications and Architectures, International Journal of Parallel Programming, volume 37, number 4, pages 343-344, 2009.
M1 Prabhat Mishra, Processor Validation: A Top-Down Approach, IEEE Potentials, February/March 2005.