Integration of Lossless Compression and Embedded Encryption

Overview

Embedded systems are constrained by the available memory. Code-compression techniques address this issue by reducing the code size of application programs. It is a major challenge to develop an efficient code-compression technique that can generate substantial reduction in code size without affecting the overall system performance. Code compression significantly improves the compression efficiency without introducing any decompression penalty. Another aspect that code compression improves is the overall execution time of the application. Fetching instructions and data from the main memory to processor incurs a significant number of clock cycles. Thus the reduced code size resulting from compression results in a reduction of the overall execution cycles, if fast decompression is done between the memory and the processor on the fly.

Code encryption can be a very useful technique in the realm of security. By encrypting text and the data segments the logic and code of the application could be made irretrievable by reverse engineering the binary executable's text or data segment or even by tracing reading the instruction from program respective process' memory space. To run the application, again, on the fly decryption is done between the memory and the processor. This way the application the safely protected from intellectual property theft or malicious manipulation of the program segments. However, run-time decryption of the code will cause a large overhead as encryption and decryption techniques are invariably heavy.

Integration of code compression with code encryption will give the added benefit of the reduced code size to fetch and decrypt, besides security.This research will explore various architectural configuration to achieve efficient execution of encrypted and compressed code. It will also be used to survey, analyze and formulate various encryption and compression techniques to the same effect.


Members


Faculty (PI): Prof. Prabhat Mishra
Graduate Students: Kamran Rahmani, Kanad Basu, Xiaoke Qin, Hadi Hajimiri, Kartik Shrivastava

Publications


Journal Articles:

J4

Kanad Basu and Prabhat Mishra, Test Data Compression using Efficient Bitmask and Dictionary Selection Methods, Accepted to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2009.

J3

Xiaoke Qin and Prabhat Mishra, A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression, Accepted to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2009.

J2

Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Design and Property Decomposition Techniques, Accepted to appear in ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 4, pages , 2009.

J1

Seok-Won Seong and Prabhat Mishra, Bitmask-Based Code Compression for Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 27, no 4, pages 673-685, April 2008.


Referred Conference Papers:

C6 Kamran Rahmani, Hadi Hajimiri, Kartik Shrivastava and Prabhat Mishra, Synergistic Integration of Code Encryption and Compression in Embedded Systems, ACM Great Lakes Symposium on VLSI (GLSVLSI), Salt Lake City, USA, May 3-4, 2012.

C5

Chetan Murthy and Prabhat Mishra, Lossless Compression using Efficient Encoding of Bitmasks, Accepted to appear in IEEE International Symposium on VLSI (ISVLSI), pages -, Tampa, Florida, USA, May 13-15, 2009.

C4

Chetan Murthy and Prabhat Mishra, Bitmask-based Control Word Compression for NISC Architectures, Accepted to appear in ACM Great Lakes Symposium on VLSI (GLSVLSI), pages -, Boston, USA, May 10-12, 2009.

C3

Xiaoke Qin and Prabhat Mishra, Efficient Placement of Compressed Code for Parallel Decompression, International Conference on VLSI Design, pages 335-340, New Delhi, India, January 5-9, 2009.

C2

Heon-Mo Koo and Prabhat Mishra, Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 137-142, Atlanta, USA, October 19 - 24, 2008.

C1

Kanad Basu and Prabhat Mishra, A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 83-88, Orlando, USA, May 4 - 6, 2008.

Research Sponsors

National Science Foundation This project is funded by the National Science Foundation (NSF). The views expressed on the site are those of the members of this project and do not necessarily represent those of the National Science Foundation.