Effective Utilization of Assertions for SoC Trust Validation |
Overview
Secure computation and trusted communication are essential as intelligent computing devices are embedded in every possible device in our daily life such as smart phones, electronic gadgets, and wearable devices. Cars are full of them, as are airplanes, satellites, and advanced military and medical devices. Any failure of security and trust requirements of these devices may endanger human life and environment by causing damages to critical infrastructure, violating personal privacy, or undermining the credibility of a business. Modern computing devices are designed using System-on-Chip (SoC) technology. Therefore, effective and well-developed hardware security validation and verification techniques need to ensure that the underlying SoC is trustworthy. The goal of this proposal is to develop automated tools and techniques to drastically reduce the overall SoC trust validation effort through effective utilization of security assertions and synthesized checkers.
While assertion-based validation is widely used, there are limited prior efforts in defining and monitoring SoC security vulnerabilities. Given the importance of SoC security in trustworthy systems, we propose a framework for defining and utilizing SoC security assertions. Specific objectives of this proposal are: i) SoC vulnerability analysis, ii) automated generation of synthesizable security assertions to monitor SoC vulnerabilities, iii) directed test generation for activating security assertions, iv) post-silicon security analysis through cost-effective synthesized checkers, v) dynamic refinement of security assertions, and vi) benchmarking and evaluation using heterogeneous SoCs.
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This project is funded by Edaptive Computing (Edaptive). The views expressed on the site are those of the members of
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