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Design-for-Debug Architecture for Post-Silicon Security Validation

Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design/verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of SoC computing platforms. Based on Common Vulnerability Exposure (CVE-MITRE) estimates, if hardwarelevel vulnerabilities are removed, the overall system vulnerability will reduce by 43%. Clearly, there is a critical need to automatically detect SoC security vulnerabilities in modern SoCs and mitigate them. While the existing efforts have shown promising results in dealing with pre-silicon IP-level trust validation, they have three major drawbacks. First, they are not applicable for post-silicon security validation since they are not designed to deal with controllability and observability constraints in fabricated chips. Next, the existing approaches primarily target malicious modifications, which represent only one out of many classes of vulnerabilities outlined in the US National Vulnerability Database. Finally, a vast majority of complex security vulnerabilities cannot be detected at pre-silicon stage for two reasons: (i) certain electrical behaviors as well as side-channel interactions cannot be accurately modeled, and (ii) detecting a complex vulnerability can take weeks or even months of pre-silicon simulation, which can be done in few minutes during post-silicon execution. The proposed research will address the above challenges to enable efficient post-silicon validation of SoC security vulnerabilities.

The above figure shows SoC design life cycle. The proposed research would make four fundamental contributions that represent a paradigm shift in post-silicon security validation. (1) Unlike existing post-silicon validation approaches that target functional validation of SoCs using well-defined error (fault) models, the proposed approach needs to verify security (non-functional) vulnerabilities without any formal threat model or well-defined security metric. (2) Compared to existing post-silicon security validation approaches that are ad-hoc and requires manual intervention of experienced designers, we propose a fully automated approach for SoC vulnerability analysis using security assertions. (3) To address the observability constraints in post-silicon debug, the proposed approach will develop an effective Design-for-Debug (DfD) architecture utilizing trace buffer, scan chains, and synthesized checkers. (4) In order to address controllability constraints associated with complex vulnerabilities (e.g., hardware Trojan in an extremely rare transition), we propose to utilize side-channel analysis for vulnerability detection by effectively analyzing side channel signatures (e.g., dynamic current). Specifically, the proposed research will develop automated tools and techniques for (i) SoC vulnerability analysis, (ii) automated generation of security assertions and synthesized checkers, (iii) observability-aware test generation for activating security vulnerabilities, (iv) development of an effective DfD architecture, and (v) side-channel analysis to detect security vulnerabilities when simulation fails to fully activate the vulnerability. This project is expected to reduce the overall SoC security validation effort by several orders of magnitude. The following figure shows the the major steps in our proposed SoC security validation methodology.

	Faculty (PI)		Graduate Students		Research Experience for Undergraduates
	Prof. Prabhat Mishra		Yangdi Lyu		Irelis Suarez
			Zhixin Pan		Andrew Whigham

Stay tuned ...



Books:

B1	Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, System-on-Chip Security Validation and Verification, ISBN: 978-3-030-30596-3, Springer, 2019.

PhD Dissertations:

D1	Yangdi Lyu, Test Generation for System-on-Chip Security Validation, Ph.D. Dissertation, University of Florida, April 2020.

Journal Articles:

J2	Yangdi Lyu and Prabhat Mishra, Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
J1	Yangdi Lyu and Prabhat Mishra, Scalable Concolic Testing of RTL Models, IEEE Transactions on Computers (TC), 2020.

Referred Conference Papers:

C4	Yangdi Lyu and Prabhat Mishra, Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis, Design Automation and Test in Europe (DATE), Grenoble, France, March 9 - 13, 2020.
C3	Yangdi Lyu and Prabhat Mishra, Automated Trigger Activation by Repeated Maximal Clique Sampling, Asia and South Pacific Design Automation Conference (ASPDAC), Beijing, China, January 13 - 16, 2020.
C2	Yangdi Lyu and Prabhat Mishra, Automated Test Generation for Activation of Assertions in RTL Models, Asia and South Pacific Design Automation Conference (ASPDAC), Beijing, China, January 13 - 16, 2020.
C1	Yangdi Lyu and Prabhat Mishra, Efficient Test Generation for Trojan Detection using Side Channel Analysis, Design Automation and Test in Europe (DATE), Florence, Italy, March 25 - 29, 2019.

Patents and Copyrights:

P3	Prabhat Mishra and Yangdi Lyu, Delay-based Side-channel Analysis for Trojan Detection, U.S. Provisional Patent Application Serial No. 62/966,657, filed January 28, 2020.
P2	Prabhat Mishra and Yangdi Lyu, Maximization of Side-Channel Sensitivity for Trojan Detection, U.S. Utility Patent Application Serial No. 16/893,696, filed June 5, 2020.
P1	Prabhat Mishra and Yangdi Lyu, Trigger Activation by Repeated Maximal Clique Sampling, U.S. Utility Patent Application Serial No. 16/893,701, filed June 5, 2020.

This project is funded by the National Science Foundation (NSF). The views expressed on the site are those of the members of this project and do not necessarily represent those of the National Science Foundation.

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