Lectures 23 & 24 Homework

[2 points] Analysis. Using a mathematical tool such as Mathematica, Matlab, or Maple, show (either analytically, numerically, or by graphing) that the exact formula for energy dissipation when charging capacitance C to voltage V through resistance R via a linear ramp over time t (shown in today's lecture) converges to the expressions CV²RC/t and CV²/2 in the low-speed (t approaching infinity) and high-speed (t approaching 0) limits, respectively.
[20 points] Small computer-based project. Construct a simulation of some simple adiabatic circuits in your favorite circuit design/simulation tool. Some students may have access to the Cadence and HSPICE or PSPICE installations in the ECE department. B2 Spice A/D is another freely available tool. (Plain Verilog or VHDL logic-level simulations will probably not be good enough to distinguish between normal and adiabatic circuits.) Feel free to reuse the Cadence cells for the chips we built at MIT. Reading the documents about the various chips (Tick,FlatTop,Pendulum) may help you figure out the cells. Or, you may find it easier to just build your own cells from scratch. Using SCRL, or 2LAL (discussed in Lec. 24), or any other fully-adiabatic style that really works (WARNING: Many "adiabatic" logic styles in the literature are broken, i.e., are not fully adiabatic), build several individual gates (including some gates that are more complex than an inverter), and some higher-level structures combining several gates (e.g., full adder cell), and test them in simulation with appropriate power supply waveforms, and graph the current waveforms coming from the power supply, and between internal nodes to make sure there are no current spikes anywhere in the circuit. (To calculate total power dissipation, you would need to integrate I*V coming from all power inputs; over a complete cycle it should be close to zero - more so as the cycle gets longer.) For 5 points extra, simulate a small sequential circuit (a reversible finite-state machine) that recycles its outputs to its inputs over several complete cycles of operation.
[100 points] Major software design project. (Race assignment.) Do a detailed software design and implementation of a symbolic (logic-level) circuit simulation tool that verifies whether a given CMOS circuit (with specified input waveforms) operates in a fully adiabatic mode, or not. This is much easier than a full analog simulation, because all transitions are between a finite set of discrete voltage levels, and occur over definite (externally controlled) timespans determined by the voltage ramps in the input waveform. Precise node capacitances and path resistances are unimportant, because in the adiabatic limit, they do not affect timing. All that is needed is to discretize time to a fraction of the ramp time, and treat transistors as ideal voltage-controlled switches with a discrete threshold, and then check at every time step to see if any of the rules for adiabatic transistor circuits (discussed in lecture) are violated. Validate your model against several known fully-adiabatic and non-fully-adiabatic logic styles. If you choose to do this project, I (Mike) will guide you further regarding the requirements & the high-level design.
[100 points] Original, creative research. (Race assignment.) Invent a fully-adiabatic, pipelineable CMOS logic style that improves upon one of the best known styles such as SCRL and 2LAL in at least one of the following respects (and does no worse in the other respects):

Number of distinct power/clock inputs required.
Number of clock "ticks" (transition times) per complete sequential cycle.
Number of transistor-ticks required per gate operation (both inverting and non-inverting gate operations).
Number of transistors for a minimal reversible gate.

[10 points] Find a paper or papers on one adiabatic logic family other than SCRL or 2LAL. A good way is to use IEEE Xplore's search page (http://ieeexplore.ieee.org/lpdocs/epic03/VSearch.htm), and search for anything containing the word "adiabatic" in the title, abstract or subject. Understand the technique, and write a short report (e.g. ~3 pages) explaining it. Compare & contrast the technique with SCRL & 2LAL. Is it fully adiabatic? Does it avoid diodes? Does it really obey all the transistor rules for fully-adiabatic logic? Can it be pipelined? What are its minimum number of ticks per logic stage, number of ticks per cycle, number of transistor-ticks per inverter, and per minimal inverting & non-inverting logic gates, and how does all these figures compare to SCRL & 2LAL? What are its minimum number of power/clock signals, and the size of its gates? So far, I have seen no fully-adiabatic, pipelinable techniques that clearly beat 2LAL and all the versions of SCRL, but maybe you will find one. (If you do, please email me.)